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1 ? isl6549 single 12v input supply dual regulator ? synchronous rectified buck pwm and linear power controller the isl6549 provides the power control and protection for two output voltages in high-performance applications. the dual-output controller drives two n-channel mosfets in a synchronous rectified buck converter topology and one n-channel mosfet in a linear configuration. the controller is ideal for applications where regulation of both the processing unit and memory supplies is required. the synchronous rectified buc k converter incorporates simple, single feedback loop, voltage-mode control with fast transient response. both the switching regulator and linear regulator provide a maximum static regulation tolerance of 1% over line, load, and temperature ranges. each output is user-adjustable by means of external resistors. an integrated soft-start feature brings both supplies into regulation in a controlled mann er. each output is monitored via the fb pins for undervoltage events. if either output drops below 75% of the nominal outpu t level, both converters are shut off and go into retry mode. the isl6549 is available in a 14 ld soic package, 16 ld qsop, or 16 ld 4x4 qfn packages. related literature ? technical brief tb363 guidelines for handling and processing moisture sensitive surface mount devices (smds) features ? single 12v bias supply (no 5v supply is required) ? provides two regulated voltages - one synchronous rectified buck pwm controller - one linear controller ? both controllers drive low cost n-channel mosfets ? small converter size - adjustable frequency 150khz to 1mhz - small external component count ? excellent output voltage regulation - both outputs: 1% over temperature ? 12v down conversion ? pwm and linear output voltage range: down to 0.8v ? simple single-loop voltage-mode pwm control design ? fast pwm converter transient response - high-bandwidth error amplifier ? undervoltage fault monitoring on both outputs ? pb-free plus anneal available (rohs compliant) applications ? processor and memory supplies ? asic power supplies ? embedded processor and i/o supplies ? dsp supplies ordering information part number part marking temp. range (c) package pkg. dwg. # isl6549cb isl6549cb 0 to 70 14 ld soic m14.15 isl6549cbz (note) 6549cbz 0 to 70 14 ld soic (pb-free) m14.15 isl6549cr isl6549cr 0 to 70 16 ld 4x4 qfn l16.4x4 isl6549crz (note) 6549crz 0 to 70 16 ld 4x4 qfn (pb-free) l16.4x4 isl6549ca isl6549ca 0 to 70 16 ld qsop m16.15a isl6549caz (note) 6549caz 0 to 70 16 ld qsop (pb-free) m16.15a isl6549caza (note) 6549caz 0 to 70 16 ld qsop (pb-free) m16.15a isl6549ibz (note) 6549ibz -40 to 85 14 ld soic (pb-free) m14.15 isl6549irz (note) 6549irz -40 to 85 16 ld 4x4 qfn (pb-free) l16.4x4 isl6549iaz (note) 6549iaz -40 to 85 16 ld qsop (pb-free) m16.15a ISL6549LOW-EVAL1 evaluation board 1-5a isl6549hi-eval1 evaluation board up to 20a add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets, mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet september 22, 2006 fn9168.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2004, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn9168.2 september 22, 2006 block diagram pinouts isl6549 (soic) top view isl6549 (qfn) top view isl6549 (qsop) top view fb comp ldo_dr ldo_fb ugate vcc5 pvcc5 14 13 12 11 1 2 3 4 10 9 8 5 6 7 fs_dis gnd boot vcc12 lgate pgnd phase comp fb ldo_dr ldo_fb fs_dis boot ugate phase pgnd lgate pvcc5 vcc5 agnd vcc12 dgnd vcc12 1 3 4 15 16 14 13 2 9 6 578 metal gnd pad (bottom) 12 10 11 fb comp ldo_dr ldo_fb ugate vcc5 pvcc5 16 15 14 13 1 2 3 4 12 11 10 5 6 7 fs_dis agnd boot vcc12 lgate pgnd phase 8 dgnd 9 vcc12 phase soft-start comp ea1 vcc5 pwm ugate ldo_dr ldo_fb power-on reset (por) oscillator fb comp ea2 uv2 voltage reference restart uv1 inhibit soft-start 0.80v 0.60v lgate boot gate logic pgnd vcc12 fs_dis gnd pvcc5 dis dis 5v regulator isl6549
3 fn9168.2 september 22, 2006 simplified power system diagram typical application schematic pwm v out1 q1 q3 v out2 linear isl6549 controller controller + q2 + +12v +v in2 +v in1 gnd +v in1 v out1 ugate q1 fb comp ldo_dr q3 ldo_fb c out2 c out1 l out isl6549 v out2 + + c bp5 q2 lgate +12v c bp12 pgnd phase fs_dis boot + pvcc5 vcc5 c bp c vin1 +v in2 vcc12 + c vin2 c boot isl6549
4 fn9168.2 september 22, 2006 isl6549 absolute maximum rati ngs thermal information vcc12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +14v pvcc5, vcc5 . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +7v vcc5 (if used with external supply). . . . . . . . . . . gnd - 0.3v to +6v boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +27v phase. . . . . . . . . . . . . . . . . . . . . . . . v boot - 7v to v boot + 0.3v v boot - v phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7v ugate. . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v to v boot + 0.3v lgate . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to pvcc5 + 0.3v ldo_dr . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vcc12 + 0.3v fb, ldo_fb, comp, fs_dis . . . . . . . gnd - 0.3v to vcc5 + 0.3v esd classification human body model (per jesd22-a114c) . . . . . . . . . . . . . . class 2 machine model (per eia/jesd22-a115-a) . . . . . . . . . . . . . .class b charge device model (per jesd22-c101c). . . . . . . . . . . . class iv thermal resistance ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 105 n/a qfn package (notes 2, 3). . . . . . . . . . 52 14 qsop package (note 1) . . . . . . . . . . . 110 n/a maximum junction temperature (plastic package) . . . . . . +150c maximum storage temperature range . . . . . . . . . -65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . +300c (soic - lead tips only) recommended operating conditions external supply voltage on vcc5 . . . . . . . . . . . . . . . . . . +5.0v 5% supply voltage on vcc12 . . . . . . . . . . . . . . . . . . . . . . . +12v 10% ambient temperature range (c). . . . . . . . . . . . . . . . . . 0c to 70c ambient temperature range (i) . . . . . . . . . . . . . . . . -40c to +85 junction temperature range. . . . . . . . . . . . . . . . . . . 0c to +125c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise noted. vcc12 = 12v temperature = 0 to +70c (typical = +25c) for commercial; temperature = -40 to + 85c (typical = +25c) for industrial. refer to block diagram, simplified powe r system diagram, and typi cal application schematic. parameter symbol test conditions min typ max units vcc supply current nominal supply current vcc12 (disabled) i cc12 dis ugate, lgate and ldo_dr open; fs_dis = gnd 23ma nominal supply current vcc5 (disabled) i cc5 dis ugate, lgate and ldo_dr open; fs_dis = gnd (note 4) 57.5ma nominal supply current vcc12 (includes pvcc5 current) i cc12 ugate, lgate and ldo_dr open; f osc = 620khz 12 18 ma nominal supply current vcc5 i cc5 ugate, lgate and ldo_dr open; f osc = 620khz 46ma maximum pvcc5 current available (note 5) i pvcc5 100 ma vcc12 to pvcc5 current limit (note 5) i pvcc5cl 150 ma pvcc5 voltage v pvcc5 isl6549c; no external load 4.95 5.25 5.8 v isl6549i; no external load 4.85 5.25 5.8 power-on reset rising vcc5 threshold vcc12 = 12v 3.7 4.2 4.5 v falling vcc5 threshold vcc12 = 12v 3.3 3.8 4.1 v rising vcc12 threshold vcc5 = 5v 8.8 9.5 10.0 v falling vcc12 threshold vcc5 = 5v 7.0 7.5 8.0 v oscillator and soft-start switching frequency f osc isl6549c; r fs_dis = 45.3k ? 540 620 700 khz isl6549i; r fs_dis = 45.3k ? 525 620 700 khz
5 fn9168.2 september 22, 2006 isl6549 sawtooth amplitude (note 6) dv osc 1.5 v soft-start interval t ss f osc = 620khz 6.8 ms reference voltage reference voltage v ref isl6549c; for error amp 1 and 2 0.792 0.8 0.808 v isl6549i; for error amp 1 and 2 0.788 0.8 0.812 v pwm controller error amplifier dc gain (note 6) r l = 10k, c l = 10pf 96 db gain-bandwidth product (note 6) gbwp r l = 10k, c l = 10pf 20 mhz slew rate (note 6) sr r l = 10k, c l = 10pf 8 v/s fb input current ? i i ? v fb = 0.8v 0.1 1.0 a comp high output voltage v out high 4.8 v comp low output voltage v out low 0.6 v comp high output, source current i out high -2.8 ma undervoltage level (v fb /v ref )v uv 70 75 80 % pwm controller gate drivers ugate maximum voltage v hugate vcc12 = 12v; phase = 12v 17 17.5 18 lgate maximum voltage v hlgate vcc12 = 12v; based on pvcc5 voltage 5.25 6 v ugate and lgate minimum voltage v l gate vcc12 = 12v; phase = 0v 0 0.5 v ugate source output impedance r ds(on) vcc12 = 12v; i gate = 100ma 0.8 ? ugate sink output impedance r ds(on) vcc12 = 12v; i gate = 100ma 0.7 ? lgate source output impedance r ds(on) vcc12 = 12v; i gate = 100ma 0.8 ? lgate sink output impedance r ds(on) vcc12 = 12v; i gate = 100ma 0.4 ? linear regulator (ldo_dr) dc gain (note 6) gain r l = 10k, c l = 10pf 100 db gain-bandwidth product (note 6) gbwp r l = 10k, c l = 10pf 2 mhz slew rate (note 6) sr r l = 10k, c l = 10pf 6 v / s ldo_fb input current ? i i ? v ldo_fb = 0.8v 0.1 1.0 a ldo_dr high output voltage v out high vcc12 = 12v 11.0 11.5 v ldo_dr low output voltage v out low 0.0 0.5 v ldo_dr high output source current i out high v out = 2.0v 2.0 ma ldo_dr low output sink current i out low 0.5 ma undervoltage level (v ldo_fb /v ref )v uv percent of nominal 70 75 80 % notes: 4. current in vcc5 is actually higher disabled, due to extra cu rrent required to pull down against the fs_dis pin. vcc12 current is lower disabled. 5. guaranteed by design, not production tested . exceeding the maximum current from pvcc5 may result in degraded performance and unsafe operation. 6. guaranteed by design, not production tested. electrical specifications recommended operating conditions, unless otherwise noted. vcc12 = 12v temperature = 0 to +70c (typical = +25c) for commercial; temperature = -40 to + 85c (typical = +25c) for industrial. refer to block diagram, simplified powe r system diagram, and typi cal application schematic. (continued) parameter symbol test conditions min typ max units
6 fn9168.2 september 22, 2006 functional pin description vcc12 this is the power supply pin for the ic; it sources the internal 5v regulator used for the gat e drivers. provide a local decoupling capacitor to gnd. the voltage at this pin is monitored for power-on reset (por) purposes. the 16 ld qfn and 16 ld qsop have two vcc12 pins; tie them together on the board. vcc5 this pin supplies the internal 5v bias for analog and logic functions. provide a local decoupling capacitor to gnd, and a resistor to pvcc. the voltage at this pin is monitored for power-on reset (por) purposes. see ?internal pvcc5 regulator? on page 7 for more details. gnd, agnd, dgnd these pins are the signal ground for the ic. all voltage levels are measured with res pect to these pins. connect all to the ground plane via the shortest available path. pvcc5 this pin is the internal 5v linear regulator for the boot supply (for the ugate driver), and the source for the lgate. provide a local decoupling capacitor to pgnd. do not use this pin as a voltage source for other circuits. see ?internal pvcc5 regulator? on page 7 for more details. pgnd this pin is the power ground return for the lower gate driver. (lgate). connect to the ground plane on the board via the shortest available path. ugate this output pin drives the upper mosfet gate from the internal 5v regulator. connect it to the gate of the upper mosfet via a short, low inductance trace. boot the boot pin, along with the external capacitor (from phase to boot), an internal diode, and the internal 5.5v regulator, creates the bootstrap voltage for the upper gate driver (ugate). the maximum voltage is around 5.5v (above phase). phase this pin represents the return path for the upper gate drive. connect it to the source of the upper mosfet via a short, low inductance trace. lgate this output pin drives the lower mosfet gate from the internal 5v regulato r. connect it to the gate of the lower mosfet via a short, low inductance trace. fb fb is the available external inverting input pin of the error amplifier. connect the output of the switching regulator to this pin through a properly sized resistor divider, to set the output voltage. the voltage at this pin is regulated to the internal reference voltage. this pin is also monitored for undervoltage detection. comp comp is the available external ou tput pin of the error amplifier. this pin is used to compensate the voltage-mode control feedback loop of the standard synchronous rectified buck converter. connect an appropr iate compensation network between this and the fb pin. see ?pwm controller feedback compensation? on page 10 for more information. fs_dis this input pin has two functions. a resistor to gnd sets the internal oscillator frequency fo r the switching regulator. in addition, if the pin is pulled down towards gnd with a low impedance (<1k ? , such as an external fet), it will disable both regulator outputs until released (at which time a new soft- start cycle will begin). ldo_dr this output pin provides th e gate voltage for the linear regulator pass transistor. connect this pin to the gate terminal of an external n-channel mosfet transistor. this pin (along with the ldo_fb pin) also pr ovides a means of compensating the error amplifier, should the application require it. ldo_fb this input pin is the fb invert ing input on the linear regulator error amplifier. connect the output of the linear regulator to this pin through a properly sized resistor divider, to set the output voltage. the voltage at this pin is regulated to the internal reference voltage. this pin is also monitored for undervoltage detection. bottom pad (qfn package only) the qfn package?s metal bottom pad is resistively tied to the internal ic gnd. for best therma l and electrical performance, connect this pad to the gnd pins, and to the ground plane of the pcb through 4 vias equidistantly situated inside the solder landing pad. isl6549
7 fn9168.2 september 22, 2006 description operation overview the isl6549 monitors and prec isely controls two output voltage levels. refer to the ?block diagram? on page 2, ?simplified power system diagram? on page 3 , and ?typical application schematic? on page 3 . the controller is intended for use in applications where only a 12v bias input is available. the ic integrates both a standard buck pwm controller and a linear controller. the pwm controller regulates the output voltage (v out1 ) to a level programmed by a resistor divider. the li near controller is designed to regulate the lower current local memory voltage (v out2 ) through an external n-channel mos pass transistor. internal pvcc5 regulator the preferred and recommended configuration is as follows: +12v to vcc12 pin, a resistor (~10 ? ) between pvcc5 and vcc5 pins, and decoupling caps on all three pins to ground. this creates the pvcc5 voltage for the gate drivers, and externally filters it for bias on the vcc5 pin. it also guarantees that all 3 voltages track each other during power-up and power-down. the pvcc5 pin cannot be used as an input and it should not be used as an output for other circuits; its current capability is reserved for the gate drivers and vcc5 bias. similarly, the vcc5 pin should not be used as an output. although not preferred, the vcc5 pin can be used with an external 5v supply (5%). however, proper precautions must be followed, which mainly have to do with pr oper sequencing, to prevent latch-up or related problems. note in the power-up diagram (figure 1), the 5v lags the 12v by a few msecs and a volt or so; that is expected. both the vcc12 and vcc5 pins must exceed their rising por trip points before the soft-start is enabled; the trip order is not im portant as long as both have some voltage. the 12v can be present with no 5v at all, but the 5v should not precede the 12v. similarly, on power down, the 5v should discharge with or before the 12v. under normal operation, the inter nal regulator can supply up to 100ma (which includes the vcc5 bias current, with the resistor between the pins). the amount of current is determined primarily by the switching parameters: the oscillator frequency and the loading of the fet gates. overloading of the internal re gulator is not recommended; even if there is enough current, the gate driver waveforms may be degraded. see ?switcher fet considerations? on page 13 for more details. the pvcc5 pin has a current limit that provides some protection against a shorted gat e driver dragging down the 12v rail. the temperature of the ic will increase as the current and corresponding on-chip powe r dissipation increases. there is no thermal shutdown, so even if the current limit is effective, the ic can be subject to very high temperatures. if the current limit is exceeded, th e regulator voltage will likely collapse, shutting down everything until the load current is reduced or removed. initialization the isl6549 automatically initializes upon application of input power (at the vcc12) pin. the isl6549 creates its own pvcc5 and vcc5 supplies for internal use. the por function continually monitors the input bias supply voltage at the vcc12 and vcc5 pins. the por function initiates soft- start operation after both these supply voltages exceed their por rising threshold voltages. soft-start the por function initiates the digital soft-start sequence. both the linear regulator error amplifier and pwm error amplifier reference inputs are forced to track a voltage level proportional to the soft-start voltage. as the soft-start voltage slews up, the pwm comparator regulates the output relative to the tracked soft-start voltage, slowly charging the output capacitor(s). simultaneously, the linear output follows the smooth ramp of the so ft-start function into normal regulation. figure 1 shows the soft-start sequence. both the vcc12 and vcc5 pins must be above their respective rising por trip points. in most cases, as show n here, the last one exceeding its threshold is the vcc12 around 9.5v. the ramp time is based on the internal oscillator period multiplied by 4096. so for a 600khz (1.67s) example, the soft-start ramp time would be 6.8ms. figure 2 shows more detail of the output ramps, by increasing the time and voltage resolution. the clock for the dac producing the steps is approximate ly 9.4khz (600khz/64), so each step is just over 100s long. the step voltage is 1/64 of the final value for each output; around 31mv for v out1 and 15.6mv for v out2 in this example. by providing many small steps of voltage (and current) that effectively charge the output capacitor, the potentially large peak current resulting from a sudden, uncontrolled voltage rise are eliminated, by spreading it out over the whole ramp time. figure 1. 12v power-up into soft-start gnd> gnd> gnd> v out1 (1v/div) vcc12 (2v/div) gnd> vcc12 > 9.5v vcc5 (2v/div) v out2 (1v/div) isl6549
8 fn9168.2 september 22, 2006 . a few clock cycles are used for initialization to insure that soft- start begins near zero volts. the ramps are the same, whether triggered by releasing fs_dis or by exceeding the por trip levels. both outputs use the same soft-s tart ramp, and the ramp time is determined by the switching frequency. thus, there is no simple way to disable or sequence them independently, or to change the ramp rate independently of the clock. if the switcher output is alread y pre-charged to a voltage when the regulator starts up, the isl6549 will detect this condition (see figure 3). the red trace shows the normal ramp, when the output starts at gnd. t he green trace shows the case when the output is pre-charged to a voltage less than the final output. the upper or lower fet does not turn on until the soft- start ramp voltage exceeds the output; then the output starts ramping seamlessly from there. if the output voltage is pre- charged above the normal output level, as shown in the magenta trace, neither fet wil l turn on until the end of the soft-start ramp; then the output will be quickly pulled down to the final value. undervoltage protection the fb and ldo_fb pins are each monitored during converter operation by their own undervoltage (uv) comparator. if either fb voltage drops below 75% of the reference voltage (75% of 0.8v = 0.6v), a fault signal is internally generated, and the fault logic shuts down both regulators. the uv comparators are enabled when the soft-start ramp is about one-quarter (25%) done. figure 4 illustrates the protection feature responding to a uv event on v out1 . at time t0, v out1 has dropped below 75% of the nominal output voltage. both outputs are quickly shut down and the ugate and lgate stop switching immediately, but the fall time of each output is determined by the load and/or short condition on each plus the output capacitance that needs to be discharged. the soft-start function begins producing an internal soft-start ramp. the delay interval, t0 to t1, seen by the output is equivalent to one soft-start cycle. then a normal soft-start ramp of the output starts, at time t1. at the one-quarter point of the soft-start ramp (not drawn exactly to scale), the good output will have ramped one- quarter way up, while the shor ted output will presumably be lower than a quarter (depending on the magnitude of the short). once the uv comparators are enabled (at the one-quarter point) both outputs will again shut down (if the fault is still present on one of them). time t2 starts a new internal soft-start cycle, and at t3, starts a new ramp, similar to t1. this time, if we assume the short has gone away, the outputs will ramp up to t4 as they should. if the short has not gone away, then the t0, t1, t2 hiccup mode cycle will keep repeating indefinitely; this cycle time is the equivalent of 1.25 figure 2. expanded view: voltage ramp and time gnd> gnd> v out1 v out2 figure 3. pre-charged output gnd> gnd> gnd> vcc12 (2v/div) gnd> vcc12 > 9.5v v out2 no charge (1v/div) v out2 over-charged (1v/div) v out2 pre-charged (1v/div) figure 4. undervoltage protection response gnd> gnd> time v out2 (2.5v) t1 t2 t3 t0 t4 (0.5v/div) v out1 (1.5v) internal soft-start function delay interval soft-start delay soft-start delay (t1 to t2 not to scale) gnd> isl6549
9 fn9168.2 september 22, 2006 soft-start cycles (1 internal soft-start ramp cycle, plus one-quarter on the next). if either v inx voltage is not present at startup, that will cause a uv shutdown and restart cycle; similarly, if either v inx is removed after start-up, a shutdown and restart cycle will start when its output drifts down to the uv trip point. but in both cases, once the v inx is restored, the v outs will recover on the next soft-start ramp. figure 5 shows an example of the start-up, with v in1 not powered. v out2 ramps up one-quarter of the way, at which time the uv comparators are enabled. since v in1 is not present, v out1 will not be following the soft-start ramp up, and it will fail the test for uv, shutting down both outputs. it starts an internal delay time-out (equal to one soft-start interval), and then starts a new ramp. for this example, it shows about a 1.6ms ramp up, and 6.4ms off, before the next ramp starts. thus, the total period of 8ms is based on 1.25 soft-start cycles (one-quarter of the first ramp, and then one full time-out, at a clock period of around 1.6s) the dotted magenta line shows the case where v out2 is allowed to ramp all of the way up to 2v. switching frequency the switching frequency of the isl6549 is determined by the value of the fs resistor. the graph in figure 6 shows the dependence between the resistor chosen and the resulting switching frequency. output voltage selection the output voltage of the pwm converter can be programmed to any level between v in1 and the internal reference, 0.8v. however, even though the isl6549 can run at near 100% duty cycle at zero load, additional voltage margin is required above v in1 to allow for loading. an external resistor divider is used to scale the output voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier (see figure 7). a typical value for r1 may be 1.00k ? (1% for accuracy), and then r4 (also 1%) is chosen according to equation 1: r1 is also part of the compensation circuit (see ?pwm controller feedback compensation? on page 10 for more details), so once chosen for that, it should not be changed to adjust v out1 ; only change r4. if the output voltage desired is 0.8v, simply route v out1 back to the fb pin through r1, but do not populate r4. v out1 voltages less than the 0.8v reference are not available. the linear regulator output voltage is also set by means of an external resistor divider as shown in figure 8. select a value for r5 (typical 1.00k ? 1% for accuracy), and use equation 2 to calculate r6 (also 1%), where v out2 is the desired linear regulator output voltage and v ref is the internal reference voltage, 0.8v. for an output voltage of 0.8v, simply populate r5 with a value less than 5k ? and do not populate r6. v out2 voltages less than the 0.8v reference are not available. figure 5. undervoltage protection (simulated by having no vin1 on power-up) gnd> v out2 (0.5v/div) v out2 (0.5v/div) gnd> 1.6ms 6.4ms v out1 (0.5v/div) 100k 1m 10k 100k 1m r (k ? ) frequency (khz) figure 6. frequency vs fs resistor r4 r1 0.8v v out1 0.8v ? --------------------------------------- - = (eq. 1) figure 7. output voltage selection of the switcher (v out1 ) r1 c out1 v out1 r4 l out isl6549 q1 fb ugate comp r2 c1 c2 r3 c3 q2 lgate v in1 + c in1 + v out 1 0.8 1 r 1 r 4 ------- - + ?? ?? = phase r 6 r 5 0.8v v out 2 0.8v ? -------------------------------------- - = (eq. 2) isl6549
10 fn9168.2 september 22, 2006 for most situations, no external compensation is required for the linear output. see ?linear controller feedback compensation? on page 12 . for both outputs, the selection of 1% resistors may not be able to get the exact ratio desir ed for any given output voltage. if the output must be defined better, then one option is to place a much bigger resistor in parallel with r4 or r6, to lower its value. for example, a 100k ? in parallel with a 1.00k ? yields 990 ? , 1% below 1.00k ? , which gives finer resolution than the next lower size (976 ? 1%). the big resistor may not have to be 1% tolerance either. if the linear output is not re quired, connect the ldo_dr pin directly to ldo_fb pin with no other components. this will terminate the signals and keep the linear from tripping its undervoltage, which would force both outputs into retry. converter shutdown pulling and holding the fs_dis pin near gnd will shut down both regulators; almost any nfet or other pull-down device (<1k ? impedance) should work. u pon release of the fs_dis pin, the regulators enter into a soft-start cycle which brings both outputs back into regulation. the fs_dis pin requires a quiet gnd to minimize jitter. to accomplish this, the fs resistor and any pull-down devic e should be placed as close as possible to the pin, and the gnd should be kept away from the noisy fet gnd. boot capacitor, boot refresh a capacitor from the phase pin to the boot pin is required for the bootstrap circuit for the upper gate. the v in1 voltage (and thus the phase node) is allowed to go as high as a nominal 12v (10%) supply. a diode is included on the ic (anode to pvcc5 pin, cathode to boot pin), such that the pvcc5 (nominally around 5.25v) will be the bootstrap supply. in the event that the ugate is on for an extended period of time, the charge on the boot capacitor can start to sag, raising the r ds(on) of the upper fet. the isl6549 has a circuit that detects a long ugate on-time (32 oscillator clock periods), and forces the lgate to go high for one oscillator cycle, which allows the bootstrap capacitor time to recharge. pwm controller feedback compensation this section highlights the design consideration for a voltage-mode controller requiring external compensation. to address a broad range of applications, a type-3 feedback network is recommended (see figure 9). figure 10 highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable to the isl6549 circuit. the output voltage (v out ) is regulated to the reference voltage, vref. the error amplifier output (comp pin voltage) is compared with the oscillator (osc) modified saw-tooth wave to provide a pulse-width modulated wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l and c). the output filter capacitor bank?s equivalent series resistance is represented by the series resistor e. the modulator transfer function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain, given by d max v in /v osc , and shaped by the output filter, with a double pole break frequency at f lc and a zero at f ce . for the purpose of this ana lysis, l and d represent the channel inductance and its dcr, while c and e represents the total output capacitance and its equivalent series resistance. the compensation network consis ts of the error amplifier (internal to the isl6549) and the external r1-r3, c1-c3 components. the goal of the compensation network is to provide a closed loop transfer function with high 0db crossing frequency (f 0 ; typically 0.1 to 0.3 of f sw ) and adequate phase margin (better than 45 degrees). phase margin is the difference between the closed loop phase at f 0db and 180. the equations that follow relate th e compensation network?s poles, zeros and gain to the components (r1, r2, r3, c1, c2, and c3) in figure 10. figure 8. output voltage selection of the linear (v out2 ) ldo_dr ldo_fb c out2 isl6549 v out2 v in2 r5 r6 + q3 v out 2 0.8 1 r 5 r 6 ------- - + ?? ?? = + c in2 figure 9. compensation configuration for isl6549 circuit isl6549 comp c1 r2 r1 fb v diff (v out ) c2 r3 c3 f lc 1 2 lc ? ? --------------------------- = f ce 1 2 ce ?? ----------------------- - = (eq. 3) isl6549
11 fn9168.2 september 22, 2006 use the following guidelines for locating the poles and zeros of the compensation network: 1. select a value for r1 (1k ? to 5k ? , typically). calculate value for r2 for desired converter bandwidth (f 0 ). if setting the output voltage via an offset resistor connected to the fb pin, ro in figure 10, the design procedure can be followed as presented. 2. calculate c1 such that f z1 is placed at a fraction of the f lc , at 0.1 to 0.75 of f lc (to adjust, change the 0.5 factor to desired number). the higher the quality factor of the output filter and/or the higher the ratio f ce /f lc , the lower the f z1 frequency (to maximize phase boost at f lc ). 3. calculate c2 such that f p1 is placed at f ce . 4. calculate r3 such that f z2 is placed at f lc . calculate c3 such that f p2 is placed below f sw (typically, 0.5 to 1.0 times f sw ). f sw represents the switching frequency. change the numerical factor to reflect desired placement of this pole. placement of f p2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the hf ripple component at the comp pin and minimizing resultant duty cycle jitter. it is recommended a mathematical model is used to plot the loop response. check the loop gain against the error amplifier?s open-loop gain. verify phase margin results and adjust as necessary. equation 8 describes the frequency response of the modulator (g mod ), feedback compensation (g fb ) and closed-loop response (g cl ): compensation break frequency equations figure 11 shows an asymptotic plot of the dc-dc converter?s gain vs. frequency. the actual modulator gain has a high gain peak dependent on the quality fact or (q) of the output filter, which is not shown. using the above guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 against the capabilities of the error amplifier. the closed loop gain, g cl , is constructed on the log-log graph of figure 11 by adding the modulator gain, g mod (in db), to the feedback compensation gain, g fb (in db). this is equivalent to multiplying the m odulator transfer function and the compensation transfer function and then plotting the resulting gain. figure 10. voltage-mode buck converter compensation design - + e/a vref comp c1 r2 r1 fb c2 r3 c3 l c v in pwm circuit half-bridge drive oscillator e external circuit isl6549 v out v osc d ugate lgate ro phase r2 v osc r1 f 0 ?? d max v in f lc ?? --------------------------------------------- = (eq. 4) c1 1 2 r2 0.5 f lc ??? ----------------------------------------------- - = (eq. 5) c2 c1 2 r2 c1 f ce 1 ? ??? --------------------------------------------------------- = (eq. 6) r3 r1 f sw f lc ------------ 1 ? --------------------- - = c3 1 2 r3 0.7 f sw ??? ------------------------------------------------- = (eq. 7) g mod f () d max v in ? v osc ----------------------------- - 1sf () ec ?? + 1sf () ed + () c ?? s 2 f () lc ?? ++ ---------------------------------------------------------------------------------------- ? = g fb f () 1sf () r2 c1 ?? + sf () r1 c1 c2 + () ?? ------------------------------------------------------ ? = 1sf () r1 r3 + () c3 ?? + 1sf () r3 c3 ?? + () 1sf () r2 c1 c2 ? c1 c2 + ---------------------- ?? ?? ?? + ?? ?? ? ---------------------------------------------------------------------------------------------------------------------------- - ? g cl f () g mod f () g fb f () ? = where s f () , 2 fj ?? = (eq. 8) f z1 1 2 r2 c1 ?? ------------------------------- - = f z2 1 2 r1 r3 + () c3 ?? --------------------------------------------------- = f p1 1 2 r2 c1 c2 ? c1 c2 + ---------------------- ?? ---------------------------------------------- - = f p2 1 2 r3 c3 ?? ------------------------------- - = (eq. 9) isl6549
12 fn9168.2 september 22, 2006 a stable control loop has a gain crossing with close to a -20db/decade slope and a phas e margin greater than 45. include worst case component variations when determining phase margin. the mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or ex ceeding half the switching frequency. when designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, f sw . linear controller feedback compensation for most situations, no external compensation is required for the linear output. as long as the output capacitor (c out2 ) is large (>100f) and so is its esr (>20mw), then it should be stable for loads as low as 10ma up to at least 4a. if smaller values of capacitance and/or esr are desired, then special considerations may be required to add external compensation (as shown in figure 8). component selection guidelines output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by equation 10. increasing the value of induct ance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient (and usually increases the dcr of the i nductor, which decreases the efficiency). increasing the switching frequency (f sw ) for a given inductor also reduces the ripple current and voltage. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the isl6549 will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor cu rrent from an initial current value to the transient current level. during this interval, the difference between the inductor current and the transient current level must be suppli ed by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. equation 11 gives the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. with a +5v input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. output capacitors selection an output capacitor is required to filter the output and supply the load transient current. the filtering requirements are a function of the switching frequency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern microprocessors produce transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor val ues are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. and keep in mind that not all applications have the same requirements; some may need many ceramic capacitors in parallel; others may need only one. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate 0 f p1 f z2 open loop e/a gain f z1 f p2 f lc f ce compensation gain gain frequency modulator gain figure 11. asymptotic bode plot of converter gain closed loop gain 20 d max v ? in v osc --------------------------------- log 20 r2 r1 ------- - ?? ?? log log log f 0 g mod g fb g cl ? v out = ? i x esr ? i = v in - v out f sw x l ------------------------------- - v out v in --------------- - ? (eq. 10) t fall l o i tran v out ------------------------------ - = t rise l o i tran v in v out ? ------------------------------- - = (eq. 11) isl6549
13 fn9168.2 september 22, 2006 transient. an aluminum electrolytic capacitor's esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not always a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of sm all case size perform better than a single large case capacitor. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q1 turns on. place the small ceramic capacitors phys ically close to the mosfets and between the drain of upper fet q1 and the source of lower fet q2. the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement for the input capacitor of a buck regulator is approximately half the dc load current. several electrolyt ic capacitors may be needed. bootstrap capacitor selection the boot diode is internal to the isl6549, and uses pvcc5 to charge the external boot capacito r. the size of the bootstrap capacitor can be chosen by using the equations in equation 12. the last equation plugs in some typical values: n = 1; q g is 33nc, v in is 12v, v gs is 11v, ? v max = 1v. in this example, c boot 0.113f. this value is often rounded to 0.1f or 0.22f as a starting value. the bootstrap capacitors for the isl6549 can usually be rated for 6.3v. switcher fet considerations the ic was designed for nominal 12v supply for v in1 (drain of upper fet q1). however, it will work with most any voltage (from other supplies or other regulator outputs) down to around 1v, as long as the input is above the output by a sufficient margin (based on prac tical duty cycle limitations and upper fet r ds(on) constraints). for example, although the ic can function at near 100% duty cycle, the voltage drop due to the r ds(on) of the upper fet at full load current will limit the practical duty cycle to something less than 100%. so the v in1 range is roughly 1.0v up to 12v, with the v out1 range slightly below it. therefore, the fets need to be rated for drain-source breakdown above the v in1 voltage; 20v and 30v ratings are common. the isl6549 gate drivers (ugate and lgate) were designed to drive up to 2 upper and 2 lower 8 ld soic fets; when the fets are properly sized, the output currents can range from under 1a to over 20a. driving more or bigger fets is not recommended; even if ther e is enough current (from the internal pvcc5 regulator), the gate driver waveforms may be degraded. dpak fet packages can be used, but d 2 pak fets are not recommended, due to the higher inductance of the package leads. for example, the inductance in the source of the lower fet can create large negative spikes on the phase node when the ugate turns off. both the ugate and lgate vo ltages are derived from the internal pvcc5 internal regulator, typically 5.25v. ugate is only about 5.0v above phase, due to the drop in the internal boot diode charging the boot capacitor; lgate sees the full 5.25v. so both are considered ?5v? drivers; this affects the fet selection in two ways. first, the fet gate-source voltage rating can be as low as 12v (this rating is usually consistent with the 20v or 30v breakdow n chosen above). second, the fets must have a low threshold voltage (around 1v), in order to have its r ds(on) rating at v gs = 4.5v in the 10m ? -20m ? range. while some fets are also rated with gate voltages as low as 2.7v, with typical thresholds under 1v, these can cause application problems. as lgate shuts off the lower fet, it does not take much ringing in the lgate signal to turn the lower fet back on, while the upper fet is also turning on, causing some shoot-through current. so avoid fets with thresholds below 1v. another set of important pa rameters are the turn-on and turn-off times (internal propagation delays, how long before the output starts to switch) and the rise and fall times (external delay to complete the switching). the ugate and lgate drivers use an adaptive technique to determine the dead time (when both gate drivers signals are low). comparators sense when each driver is getting close to gnd (such that its fet is close to being off), before turning on the other. this technique minimizes the dead time to the 10ns-20ns range. so if either c boot q gate ? v ------------------- - q gate nq g v in ? ? v gs ---------------------------------- = c boot q gate ? v ------------------- - nq g v in ? ? v gs ? v ? ---------------------------------- 13312 ? ? 50.7 ? --------------------------- - 0.113 f = = = where n is the number of upper fets q g is the total gate charge per upper fet v in is the input voltage v gs is the gate-source voltage (~5v for isl6549) ? v is the change in boot voltage before and immediately after the transfer of charge; typically 0.7v to 1.0v and (eq. 12) isl6549
14 fn9168.2 september 22, 2006 fet is particularly slow in these parameters, there is a greater chance that shoot-through current will occur. as referenced in the ?block diagram? on page 2, the ugate signal is referenced to phase signal. the deadtime comparator also looks at the difference (uga te - phase). this is significant when viewing the gate driver waveforms on an oscilloscope. one simple indication of shoot-through (or insufficient deadtime) is when the ugate and lgate signals overlap. but in this case, on e should look at ugate-phase (either by a math function of the two signals, or by using a differential probe measurem ent) compared to lgate. figure 12 shows an example of th is. it looks as if the ugate and lgate signals have crossed, but the ugate-phase signal does not cross the lgate. one important consideration is negative spikes on the phase node as it goes low. the upper fet is turning off, but before the lower fet can take over, stray inductance in the layout (on the board, or even the i nductance of some components, such as d 2 pak fets) can contribute to the phase going negative. there is no maximum spec for phase spike below gnd, however, there is an absolute maximum rating for (boot - phase) of 7v; exceeding this limit can cause damage to the ic, and possibly to the system. since the boot signal is typically 5v above the phase node most of the time, it only takes a few volts of a spike on either signal to exceed the limit. a good design should be characterized by using the math function or differential probe, and monitoring these signals for compliance, especially during full loads, where the signals are usually the noisiest. slowing down the turn-off of the upper fet may help, while at other times, sometimes the problem may just be the choice of fets. if the power efficiency of the system is important, then other fet parameters are also consid ered. efficiency is a measure of power losses from input to output, and it contains two major components: losses in the ic (m ostly in the gate drivers) and losses in the fets. optimi zing the sum involves many trade-offs (for example, raising the voltage of the gate drivers typically adds power to the ic side, but may reduce some power on the fet side). for low duty cycle applications (such as 12v in to 1.5v out), the up per fet is usually chosen for low gate charge, since switching losses are key, while the lower fet is chosen for low r ds(on) , since it is on most of the time. for high duty cycles (such as 3.3v in to 2.5v out), the opposite is true. in summary, the following parameters may need to be considered in choosing the right fets for an application: drain-source breakdown voltage rating, gate-source rating, maximum current, thermal and package considerations, low gate threshold voltage, gate charge, r ds(on) at 4.5v, and switching speed. and, of cour se, the board layout constraints and cost also are factored into the decision. linear fet considerations the linear fet is chosen primar ily for thermal performance. the current for the linear output is generally limited by the power dissipation (p = (v in2 - v out2 ) * i), and the fet thermal rating for getting the heat out of the package, and spreading it out on the board, especially when no heatsinks or airflow is available. it is generally not recommended to parallel two fets in order to get higher current or to spread out the heat, as the fets would need to be very well-matched in order to share the current pr operly. should this approach be desired, and as perfectly matched fets are seldom available, a small resistor, or pcb trace of suitable resistance placed in the source of each of the fe ts can be used to improve the current balance. the maximum v out2 voltage allowed is determined by several factors: ? power dissipation, as described earlier ? input voltage available ? ldo_dr voltage ? fet chosen the voltage cannot be any higher than the input voltage available, and the max v in2 is 12v (13.2v for a 10% supply). the ldo_dr voltage is driven from the vcc12 rail; allowing for headroom, the typical maximum voltage is 11v (lower as vcc12 goes to its minimum of 10.8v). so the maximum output voltage will be at least a v gs drop (which includes the fet threshold voltage) below the 11v, at the maximum load current; some additional headroom is usually needed to handle transient conditions. so a practical typical value around 8v may be possible, but remember to also factor in the variations for worst case conditions on v in2 and the fet parameters. as long as the v in2 is low enough such that headroom versus vcc12 is not a problem, then the maximum output voltage is just below v in2 , based on the r ds(on) drop at maximum current. the input supply for v in2 can also be any available supply less than 12v, subject to the considerations above. the drain-source breakdown voltage of the fet should be greater figure 12. gate driver waveforms ugate (4v/div) ugate-phase (4v/div) phase (4v/div) lgate (4v/div) gnd> gnd> gnd> gnd> isl6549
15 fn9168.2 september 22, 2006 than the v in2 voltage. the fet?s gate-source rating should be greater than 12v (even though the output voltage may not require such a high gate voltage, load transients or other disturbances might force ldo_dr to momentarily approach 12v). the fet threshold is not critical, except for the cases where the ldo_dr headroom is diminished. and finally, the package (and board area allowed) must be able to handle the maximum power dissipation expected. application guidelines layout considerations layout is very important in high frequency switching converter design. with power devices switching efficiently at 600khz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit board design minimizes the voltage spikes in the converters. as an example, consider the turn-off transition of the pwm upper mosfet. prior to turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the upper mosfet and is picked up by the lower mosfet and parasitic diode. any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and shor t, wide traces minimizes the magnitude of voltage spikes. there are two sets of critical components in a dc/dc converter using the isl6549. the switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large am ounts of noise. next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. a multilayer printed circuit board is recommended. figure 13 shows the connections of the critical components in the converter. capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually a middle layer of the pc board, for a ground plane and make all critical component ground connections through vias to this layer. dedicate another solid layer as a power plane and break this plane into smal ler islands of common voltage levels. keep the metal runs from the phase terminal to the output inductor short. the power plane should support the input and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase node. use the remaining printed circuit layers for small signal wiring. the wiring traces from the lgate and ugate pins to the mosfet gates should be kept short and wide enough to easily handle the several amps of drive current. the critical small signal components include any bypass capacitors, feedback components, and compensation components. position the bypass capacitors, c 4 , c 5 , and c 6 close to their pins with a local gnd connection, or via directly to the ground plane. r12 should be placed near vcc5 and pvcc5 pins. fs_dis resistor r7 should be near the fs-dis pin, and its gnd return should be short, and kept away from the noisy fet gnd. place the pwm converter compensation components close to the fb and comp pins. the feedback resistors for both regulators should also be located as close as possible to the relevant fb pi n with vias tied straight to the ground plane as required. then the switching components should be placed close to the isl6549. minimize the length of the connections between the input capacitors, c in , and the power switches by placing them nearby. position both the ceramic and bulk input capacitors as close to the upper mosfet drain as possible, and make the gnd returns (from lower fet s ource to vin cap gnd) short. position the output inductor and output capacitors between the upper mosfet and lower mosfet and the load. references applications note: an1201 visit us on the internet: www.intersil.com figure 13. printed circuit board power planes and islands v out1 vcc5 island on power plane layer island on circuit plane layer l out c out1 c in1 v in1 key comp isl6549 ugate r 4 r 2 c 5 fb ldo_dr gnd vcc5 r1 v out2 ldo_fb c 2 via connection to ground plane c out2 load load q1 v in2 r5 r6 phase r 3 c 3 c 1 q2 vcc12 c 4 gnd vcc12 q3 lgate c in2 pvcc5 c 6 pgnd pvcc5 r12 boot c 7 fs_dis r 7 isl6549
16 fn9168.2 september 22, 2006 isl6549 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.35 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 1.95 2.10 2.25 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 1.95 2.10 2.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 5 5/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
17 fn9168.2 september 22, 2006 isl6549 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not ex ceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9168.2 september 22, 2006 isl6549 shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. converted millimeter dimen- sions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m b s e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m16.15a 16 lead shrink small outline plastic package (0.150? wide body) symbol inches millimeters notes min max min max a 0.061 0.068 1.55 1.73 - a1 0.004 0.0098 0.102 0.249 - a2 0.055 0.061 1.40 1.55 - b 0.008 0.012 0.20 0.31 9 c 0.0075 0.0098 0.191 0.249 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.81 3.99 4 e 0.025 bsc 0.635 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.89 6 n16 167 0 8 0 8 - rev. 2 6/04

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